(1) Field of the Invention
The present invention relates to a system for processing machine check interruption and more particularly to a system for processing machine check interruption using a data processor in which a machine check interruption code is analyzed when a machine check interruption occur. If the contents of the machine check interruption code show a condition in which the operation of the hardware thereafter is not guaranteed, the data processor is placed in a disabledwaiting condition.
(2) Description of the Prior Art
In a data processor, there are two main causes of machien check interruptions. One is an "exigent" condition which greatly damages the system of the data processor, and the other is a "repressible" condition which is recovered by a re-try. In an exigent condition, the central processing unit (CPU) is directly damaged, and, therefore, it becomes impossible to proceed with the execution of the instructions and with the processing of the interruption. An exigent condition is of two types: instruction processing damage (PD) and system damage (SD). An erroneous operation which cannot be discriminated as a specific kind of condition is indicated as SD. The SD includes SD occurring on a memory access route and SD occurring on a CPU route.
In a data processor, jobs are generally executed under the management of the operating system. When the jobs are executed, if the above-mentioned SD occurs, the interruption processing for the above-mentioned machine check is carried out by the software. The SD also includes damage which makes the operation of hardware unreliable, for example, damage resulting in the erroneous operation of a memory control unit (MCU) which controls the memory access operation. However, the software sometimes does not judge such damage to be in a system breakdown condition when the cause thereof is a certain kind, but executes the processing so as to interrupt, i.e., to end abnormally, only the job at that time and to move on to the next job. However, if a SD machine check error occurs in the MCU, for example, if an address parity error occurs in a main storage unit (MSU) when data is written into the MSU, the execution of subsequent jobs is not guaranteed. In this case, since the software executes some processing, it appears as if correct processing is carried out although the result of the execution is not guaranteed. Therefore, there is the danger of trouble, such as an unexpected change of the processed data, occurring.
it is desirable that the hardware immediately assume a check-stop condition when the above-mentioned erroneous operation occurs. In conventional hardware, however, since rendering the hardware to be in the check-stop mode is controlled for every type of SD in any portion, i.e., SD in the CPU, SD in the MCU, or SD in another portion. leads to the same check-stop condition. Therefore, an erroneous operation in the CPU having the SD, which usually does not lead to a system breakdown, this time does lead to a system breakdown, and the data processing is disturbed. It is also possible to design the system so that the check-stop mode is deactivated and the system breakdown condition does not occur due to a machine check interruption of the SD type. In this case, however, when SD occurs in the MCU, for example, when an address parity error is detected in the write-in operation to the main storage unit, processing is executed on the basis of erroneous data and the result obtained by processing is not guaranteed.